An 8-bit TDC implemented with two nested Johnson counters
Article Sidebar
Main Article Content
Abstract
This work presents a Time-to-Digital Converter implemented using two nested Johnson counters and suitable for time-lapse measurement applications. The proposed structure is composed of two 4-bit nested counters, two digital-logic control networks, two registers and a single decoder. Semi-dynamic logic was used for the decoder to reduce its power consumption. The system has a standard digital output and is powered by a 1.8 V supply with a total power consumption of 32.4 mW. A prototype was fabricated using a TSMC 180 nm CMOS technology. The proposed structure uses a 508 µm x 225 µm area. In addition, this TDC has a standard deviation of 0.78 LSB with a fixed input time interval operating at a frequency of 1 MHz. The proposed structure shows good performance results and repeatability for continuous conversion conditions, these results are attributed to the simplicity of the system and the use of counters with minimum gate delay as the main elements for the TDC.
Article Details
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
Los autores conservan los derechos de autor y ceden a la revista el derecho de la primera publicación y pueda editarlo, reproducirlo, distribuirlo, exhibirlo y comunicarlo en el país y en el extranjero mediante medios impresos y electrónicos. Asimismo, asumen el compromiso sobre cualquier litigio o reclamación relacionada con derechos de propiedad intelectual, exonerando de responsabilidad a la Editorial Tecnológica de Costa Rica. Además, se establece que los autores pueden realizar otros acuerdos contractuales independientes y adicionales para la distribución no exclusiva de la versión del artículo publicado en esta revista (p. ej., incluirlo en un repositorio institucional o publicarlo en un libro) siempre que indiquen claramente que el trabajo se publicó por primera vez en esta revista.
References
Moore, Gordon E. “No exponential is forever: but “Forever” can be delayed![semiconductor industry].” In 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., pp. 20-23. IEEE, 2003.
Staszewski, Robert Bogdan, Khurram Muhammad, Dirk Leipold, Chih-Ming Hung, Yo-Chuol Ho, John L. Wallberg, Chan Fernando et al. “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS.” IEEE Journal of Solid-State Circuits 39, no. 12 (2004): 2278-2291.
Porat, Dan I. “Review of sub-nanosecond time-interval measurements.” IEEE Transactions on Nuclear Science 20, no. 5 (1973): 36-51.
Mandai, Shingo, Vishwas Jain, and Edoardo Charbon. “A $780 X 800 µm2 Multichannel Digital Silicon Photomultiplier With Column-Parallel Time-to-Digital Converter and Basic Characterization.” IEEE Transactions on Nuclear Science 61, no. 1 (2014): 44-52.
Faramarzpour, Naser, M. Jamal Deen, Shahram Shirani, and Qiyin Fang. “Fully integrated single photon avalanche diode detector in standard CMOS 0.18-µm Technology.” IEEE Transactions on electron devices 55, no. 3 (2008): 760-767.
Rai, Abhishek, and Rajesh Mehra. “Optimized Design and Simulation of 4-Bit Johnson Ring Counter Using 90nm Technology.” International Journal of Research in Advent Technology 16, no. 6 (2018): 1002-1006.
Kumar, Sandeep, M. K. Suman, and K. L. Baishnab. “A novel approach to thermometer-to-binary encoder of flash ADCs-bubble error correction circuit.” In 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS), pp. 1-6. IEEE, 2014.